1. Field of the Invention
The present invention relates to a memory management device that manages access to a memory.
2. Description of the Related Art
In a conventional information processing device, a volatile semiconductor memory, for example, a DRAM (Dynamic Random Access Memory) is used as a main memory device of a processor. Further, in a conventional information processing device, a nonvolatile semiconductor memory is used as a secondary storage device in combination with the volatile semiconductor memory.
Jpn. Pat. Appln. KOKAI Publication No. 2008-242944 (Patent Literature 1) proposes an integrated memory management device. In the integrated memory management device, a NAND flash memory is used as a main memory for an MPU. Further, in Patent Literature 1, a primary cache memory of the MPU, a secondary cache memory, and the NAND flash memory, which is the main memory, are handled in the same memory layer. A cache controller of the integrated memory management device implements, in addition to memory management of the primary cache memory and the secondary cache memory, memory management of the main memory.
Jpn. Pat. Appln. KOKAI Publication No. 7-146820 (Patent Literature 2) discloses a technology that adopts a flash memory as the main memory device of an information processing device. According to Patent Literature 2, a flash memory is connected to a memory bus of a system via a cache memory, which is a volatile memory. The cache memory is provided with an address array that records information such as addresses and an access history of data stored in the cache memory. A controller references an access destination address to supply data in the cache memory or the flash memory to the memory bus or to store data in the memory bus.
Jpn. Pat. Appln. KOKAI Publication No. 2001-266580 (Patent Literature 3) discloses an invention allowing different kinds of semiconductor memory devices to connect to a common bus.
A semiconductor memory device according to Patent Literature 3 includes a random access memory chip and a package including the random access memory chip. The package has a plurality of pins to electrically connect the random access memory chip to an external device. The plurality of pins provides a memory function commonly to the random access memory chip and a nonvolatile semiconductor memory that can electrically be erased and programmed. Each of the plurality of pins is arranged in the position of a corresponding pin of the nonvolatile semiconductor memory.